Design Verification Engineers (VLSI)

• Developing and modifying full chip test plans to ensure comprehensive verification coverage.
• Designing and modifying testbenches to facilitate efficient verification.
• Developing, coding, and executing test cases while analyzing bugs and issues.
• Conducting regressions and coverage analysis to track verification progress.
• Leading verification closure activities to ensure the project meets quality standards.
• Ensuring process compliance within the assigned module and actively participating in technical discussions and reviews.
• Preparing and submitting detailed status reports to mitigate project risks and address escalations effectively.

Required Skills and Experiences:

• Bachelor's or Master’s degree in Electronics/Electrical Engineering with a minimum of 3 years of experience in verification.
• Intermediate English with the ability to communicate at basic level.
• Strong understanding of the ASIC/SoC life cycle.
• Experience in full chip test plan development and modification.
• Proficiency in testbench development/modification, test case development, coding, execution, bug analysis, regressions, coverage analysis, and verification closure.
• Familiarity with gate-level simulations.
• Proficiency in scripting languages.
• Previous involvement in multiple ASIC/SoC verifications up to the tape-out stage.
• Excellent English communication skills for effective working communication.

Preferred Skills and Experiences:

• Familiarity with industry-standard verification methodologies such as UVM.
• Experience in formal verification techniques.
• Knowledge of system-level verification methodologies.
• Familiarity with hardware description languages such as Verilog or VHDL.